1. Field of the Invention
Generally, the present disclosure relates to sophisticated semiconductor devices and the manufacturing of such devices, and, more specifically, to a novel charging controlled RRAM (Resistance Random Access Memory) device, and various methods of making such a charging controlled RRAM device.
2. Description of the Related Art
As is well known to those skilled in the art, non-volatile memory (NVM) devices are characterized in that there is no loss of data stored in their memory cells, even when an external power supply is removed. For that reason, such non-volatile memory devices are widely employed in computers, mobile communication systems, memory cards and the like.
Flash memory structures are widely used in such non-volatile memory applications. The typical flash memory device employs memory cells having a stacked gate structure. The stacked gate structure typically includes a tunnel oxide layer, a floating gate, an inter-gate dielectric layer and a control gate electrode, which are sequentially stacked above a channel region. While flash memory structures have enjoyed enormous success, the continued and ever-present drive to reduce the size of integrated circuit products has created many challenges for the continued scaling of flash memory devices. Such challenges include scaling of program/erase voltages, access speed, reliability, the number of charges stored per floating gate, etc.
A resistance random access memory (RRAM) device is a simple two-terminal device memory device comprised of two spaced-apart electrodes with a variable resistance material layer or ion conductor layer positioned between the two electrodes. The variable resistance material layer is typically comprised of various metal oxides, such as nickel oxide, titanium oxide, zirconium oxide, copper oxide, aluminum oxide, etc. The variable resistance material layer is used as a data storage layer. The resistance of the variable resistance material layer may be varied or changed based upon the polarity and/or amplitude of an applied electric pulse. The electric field strength or electric current density from the pulse, or pulses, is sufficient to switch the physical state of the materials so as to modify the properties of the material and establish a highly localized conductive filament (CF) in the variable resistance material. The pulse is of low enough energy so as not to destroy, or significantly damage, the material. Multiple pulses may be applied to the material to produce incremental changes in properties of the material. One of the properties that can be changed is the resistance of the material. The change may be at least partially reversible using pulses of opposite polarity or pulses having a different amplitude from those used to induce the initial change.
In general, after an RRAM device is initially fabricated, the variable resistance material layer does not exhibit any switching properties. Rather, a so-called FORMING process, a high-voltage, high-current process, is performed to initially form the localized conductive filament with oxygen vacancies from the cathode, establishing a low-resistance state (LRS) exhibiting a relatively high current flow. A so-called RESET process is performed to break the conductive filament and establish a high-resistance state (HRS) exhibiting a relatively low current flow. This RESET process is typically a current-driven thermal process that causes the conductive filament to be broken by a heat-assisted chemical reaction. More specifically, the conductive filament is broken due to the fact that a high current is passing through an ultra-thin (a few nanometers) conductive filament causing a high current density which leads to high temperatures and a melting down of the conductive filament. Note that the RESET process removes only a portion of the entire length of the conductive filament, i.e., the RESET process does not remove the entire conductive filament. After a RESET process is performed, a so-called SET process is performed to reestablish the conductive filament and thus the low-resistance state of the charging controlled RRAM device. The SET process is essentially the same as the FORMING process except that the SET process is performed at a lower voltage than the FORMING process since the filament length to be reestablished is shorter than the length of the conductive filament that was formed during the FORMING process.
One problem associated with a traditional RRAM device is the relatively high power required to initially form the localized conductive filament in the variable resistance material layer during the FORMING process. For example, in some current-day RRAM devices, it may take up to approximately 0.2 W of power to initially form the conductive filament. Such a large power requirement for forming the conductive filament is not only wasteful, it is highly incompatible with the scaling of semiconductor devices, such as those employing CMOS technology, and particularly in mobile applications, such as cell phones and the like, where power conservation and battery life is a very important consideration. It is believed that this requirement of a relatively high power to form the conductive filament in an RRAM device has limited the widespread adoption of RRAM devices in integrated circuit products.
One example of a well-established non-volatile memory product is so-called Flash memory devices. Flash memory devices have been in widespread use since their development in the 1990's. In general, a Flash memory cell is comprised of two gates—a floating gate (typically polysilicon) and a control gate positioned above the floating gate. The floating gate is formed above a gate insulation layer (typically silicon dioxide) and a so-call tunnel oxide layer is formed between the floating gate and the control gate. In general, a charge is stored on the floating gate and the presence or absence of such a charge is indicative of two distinct states that may be employed as a memory device. One of the states may be associated with a logical “high” state (a “1”), while the other state may be associated with a logical “low” state (a “0”). The ability of a Flash memory device to store electrical charge on the floating gate is due to the inherent energy barrier (about 3.2 eV) between the polysilicon floating gate and the silicon dioxide gate insulation layer. Because of this high energy barrier, programming and erasing a Flash memory device involves relatively high voltages. Over the years, Flash memory devices have been greatly reduced in size or scaled due to a variety of factors, such as, for example, improvements in photolithography tools and techniques, and the use of various so-called self-alignment manufacturing techniques. However, reduction of the physical size of the typical Flash memory device is limited by the electrical operational characteristics of the device. For example, to achieve hot-carrier programming, a voltage of about 4V is typically required to overcome the silicon-silicon dioxide barrier energy level of about 3.2V. A Flash memory device with a channel length that is too short (e.g., less than about 70 nm) may not be able to withstand the required programming voltage that is necessary to operate a traditional Flash memory device. Alternative materials for the gate insulation layer may also help with further device scaling of Flash memory devices, but the development in that area has not been as successful as would otherwise be desired. An additional area that may be problematic in scaling Flash memory devices involves the tunnel oxide layer. In general, there must be sufficient capacitive coupling between the floating gate and the control gate so that the erase voltage can be kept as low as possible. Scaling of a Flash memory device requires that the tunnel oxide layer be reduced in thickness to maintain the desired degree of capacitive coupling between the floating gate and the control gate. Current memory devices have employed various materials or combinations of material (such as an oxide-nitride-oxide tunnel oxide) that meet today's requirements. However, as device dimensions continue to shrink, it remains to be seen whether or not the industry can continue to provide tunnel oxide layers that enable the desired level of capacitive coupling between the floating gate and the control gate.
Recently, another type of a two-terminal RRAM device has been observed that employs nano-crystals embedded in a layer of silicon dioxide. With respect to such a device, it has been observed that by charging (programming) and discharging (erasing) nano-crystals into a capacitor structure (via Fowler-Nordheim tunneling), the gate current conduction may be modulated. Each gate conduction state is well defined and represents a potential memory state. During charging (electron trapping) and discharging (electron de-trapping and/or hole trapping) causes, respectively, a reduction and enhancement in the current conduction, where the current conduction is due to electron transport. However, the two-terminal device has little appeal as it relates to current-day memory devices where high densities are required.
The present disclosure is directed to a novel charging controlled RRAM device, and various methods of making such an RRAM device.